Scaling semiconductor devices by simply shrinking the device structure often does not produce acceptable results at small dimensions. In NAND flash memory devices, when a feature, such as a tunnel oxide layer, an inter poly dielectric (IPD) layer, or the like is scaled, undesired leakage can occur between, for example, a substrate and a floating gate, a floating gate and a control gate, or the like. Accordingly, and for example, to improve the reliability of a tunnel oxide layer or to suppress dopant out diffusion of a floating gate, each layer can have nitrogen incorporated therein or at a surface thereof, such as by a nitridization process.
Typically, such a nitridation process may be performed to incorporate nitrogen into the floating gate structure of a memory device. However, the nitridation process also undesirably incorporates nitrogen into shallow trench isolation (STI) regions, which separate adjacent floating gate structures. STI regions having nitrogen incorporation may undesirably electrically couple adjacent floating gate structures, resulting in electrical coupling between adjacent floating gates which can negatively impact final device performance. In some conventional processes, a wet chemical process may be utilized to try to remove the nitrogen in the STI regions after a nitridation process. Unfortunately, however, the wet chemical removal process also removes and degrades the desired nitrogen-containing layer formed atop the floating gate.
Accordingly, there is a need in the art for improved methods of fabricating semiconductor devices.